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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD1819A one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 ac 97 soundport ? codec ac '97 features fully compliant ac 97 analog i/o component 48-terminal tqfp package multibit sd converter architecture for improved s/n ratio >90 db 16-bit stereo full-duplex codec four analog line-level stereo inputs for connection from line, cd, video and aux two analog line-level mono inputs for speakerphone and pc beep mono mic input switchable from two external sources high quality cd input with ground sense stereo line level output mono output for speakerphone power management support enhanced features support for multiple codec communications dsp 16-bit serial port format variable 7 khz to 48 khz sampling rate with 1 hz resolution supports modem sample rates and filtering phat? stereo 3d stereo enhancement vhdl and verilog models of serial port available soundport is a registered trademark of analog devices, inc. phat is a trademark of analog devices, inc. functional block diagram g a m g a m s s s g a m ac link sync bit_clk s phat stereo phat stereo s s g a m s s a m mv 0db/ 20db mv AD1819A mic1 mic2 aux cd video pc_beep line_out_l mono_out line_in phone_in line_out_r s mv selector pga pga 16-bit sd a/d converter g a m sample rate generators g = gain a = attenuate m = mute mv = master volume oscillators xtalo xtali cs1 chain_in chain_clk reset sdata_in cs0 s s s s s s s s master/slave synchronizer sdata_out g a m 16-bit sd a/d converter g a m g a m 16-bit sd d/a converter 16-bit sd d/a converter
AD1819A C2C rev. 0 product overview the AD1819A soundport codec is designed to meet all re quire- ments of the audio codec 97, component specification , revision 1.03, ? 1996, intel corporation, found at www.intel.com. in addition, the AD1819A supports multiple codec configurations (up to three per ac-link), a dsp serial mode, variable sample rates, modem sample rates and filtering, and built-in phat ste- reo 3d enhancement. the AD1819A is an analog front end for high performance pc audio, modem, or dsp applications. the ac 97 architecture defines a 2-chip audio solution comprising a digital audio con- troller, plus a high quality analog component that includes digital-to-analog converters (dacs), analog-to-digital con- verters (adcs) mixer and i/o. the main architectural features of the AD1819A are the high quality analog mixer section, two channels of sd adc conver- sion, two channels of sd dac conversion and data direct scrambling (d 2 s) rate generators. the AD1819As left channel adc and dac are compatible for modem applicati ons support- ing irrational sample rates and modem filtering requirements. functional description this section overviews the functionality of the AD1819A and is intended as a general introduction to the capabilities of the device. detailed reference information may be found in the descriptions of the indexed control registers. analog inputs the codec contains a stereo pair of sd adcs. inputs to the adc may be selected from the following analog signals: tele- phony (phone_in), mono microphone (mic1 or mic2), stereo line (line_in), auxiliary line input (aux), stereo cd rom (cd), stereo audio from a video source (video) and post-mixed stereo or mono line output (line_out). analog mixing phone_in, mic1 or mic2, line_in, aux, cd and video can be mixed in the analog domain with the stereo output from the dacs. each channel of the stereo analog in- puts may be independently gained or attenuated from +12 db to C34.5 db in 1.5 db steps. the summing path for the mono inputs (phone_in, mic1, and mic2 to line_out) dupli- cates mono channel data on both the left and right line_out. additionally, the pc attention signal (pc_beep) may be mixed with the line output. a switch allows the output of the dacs to bypass the phat stereo 3d enhancement. analog-to-digital signal path the selector sends left and right channel signals to the program- mable gain amplifier (pga). the pga following the selector allows independent gain for each channel entering the adc from 0 db to +22.5 db in 1.5 db steps. each channel of the adc is independent, and can process left and right channel data at different sample rates. all pro- grammed sample rates from 7 khz to 48 khz have a resolution of 1 hz. the AD1819A also supports irrational v.34 sample rates. sample rates and d 2 s the AD1819A default mode sets the codec to operate at 48 khz sample rates. the converter pairs may process left and right channel data at different sample rates. the AD1819A sample rate generator allows the codec to instantaneously change and process sample rates from 7 khz to 48 khz with a resolution of 1 hz. the in-band integrated noise and distortion artifacts in- troduced by rate conversions are below C90 db. the AD1819A uses a 4-bit d/a structure and data directed scrambling (d 2 s) to enhance noise immunity on motherboards and in pc enclo- sures, and to suppress idle tones below the devices quantization noise floor. the d 2 s process pushes noise and distortion arti- facts caused by errors in the multibit d/a conversion process to frequencies beyond the audible range of the human ear and then filters them. digital-to-analog signal path the analog output of the dac may be gained or attenuated from +12 db to C34.5 db in 1.5 db steps, and summed with any of the analog input signals. the summed analog signal enters the master volume stage where each channel of the mixer out- put may be attenuated from 0 db to C46.5 db in 1.5 db steps or muted. host-based echo cancellation support the AD1819A supports time correlated i/o data format by presenting mic data on the left channel of the adc and the mono summation of left and right output on the right channel. the adc is splittable; left and right adc data can be sampled at different rates. telephony modem support the AD1819A contains a v.34-capable analog front end for supporting host-based and data pump modems. the modem dac typical dynamic range is 90 db over a 4.2 khz analog output passband where f s = 12.8 khz. the left channel of the adc and dac may be used to convert modem data at the same sample rate in the range between 7 khz and 48 khz. all pro- grammed sample rates have a resolution of 1 hz. the AD1819A supports irrational v.34 sample rates with 8/7 and 10/7 select- able sample rate multiplier coefficients.
C3C rev. 0 AD1819A standard test conditions unless otherwise noted dac test condition s temperature 25 c calibrated digital supply (v dd ) 5.0 v 0 db attenuation analog supply (v cc ) 5.0 v input 0 db sample rate (f s ) 48 khz 10 k w output load input signal 1008 hz mute off analog output passband 20 hz to 20 khz adc test conditions v ih (ac-link) 2.0 v calibrated v il (ac-link) 0.8 v 0 db gain v ih (cs0, cs1, chain_in) 4.0 v input C3 db relative to full scale v il (chain_clk) 1.0 v line input selected analog input parameter min typ max units input voltage (rms values assume sine wave input) line_in, aux, cd, video, phone_in, pc_beep 1 v rms 2.83 v p-p mic1, mic2 with +20 db gain (m20 = 1) 0.1 v rms 0.283 v p-p mic1, mic2 with 0 db gain (m20 = 0) 1 v rms 2.83 v p-p input impedance* 10 k w input capacitance* 15 pf programmable gain amplifieradc parameter min typ max units step size (0 db to 22.5 db) 1.5 db pga gain range span 22.5 db analog mixer input gain/amplifiers/attenuators parameter min typ max units dynamic range (C60 db input thd+n, referenced to full scale, a-weighted) cd to line_out 90 db other to line_out* 90 db step size (+12 db to C34.5 db): (all steps tested) mic, line_in, aux, cd, video, phone_in, dac 1.5 db input gain/attenuation range mic, line_in, aux, cd, video, phone_in, dac 46.5 db step size (0 db to C45 db): (all steps tested) pc_beep 3.0 db input gain/attenuation range: pc_beep 45 db digital decimation and interpolation filters* parameter min typ max units passband 0 0.4 f s hz passband ripple 0.09 db transition band 0.4 f s 0.6 f s hz stopband 0.6 f s hz stopband rejection C74 db group delay 12/f s sec group delay variation over passband 0.0 m s *guaranteed, not tested. specifications subject to change without notice. specifications
C4C rev. 0 AD1819ACspecifications analog-to-digital converters parameter min typ max units resolution 16 bits total harmonic distortion (thd) 0.02 % C74 db dynamic range (C60 db input thd+n referenced to full scale, a-weighted) 84 87 db signal-to-intermodulation distortion* (ccif method) 85 db adc crosstalk* line inputs (input l, ground r, read r; input r, ground l, read l) C100 C90 db line to other C90 C85 db gain error (full-scale span relative to nominal input voltage) 10 % interchannel gain mismatch (difference of gain errors) 0.5 db adc offset error 5mv digital-to-analog converters parameter min typ max units resolution 16 bits total harmonic distortion (thd) line_out 0.02 % C74 db dyna mic range (C60 db input thd+n referenced to full scale, a-weighted) 85 90 db signal-to-intermodulation distortion* (ccif method) 85 db gain error (full-scale span relative to nominal input voltage) 10 % interchannel gain mismatch (difference of gain errors) 0.5 db dac crosstalk* (input l, zero r, measure line_out_r; input r, db zero l, measure line_out_l) C80 db total out-of-band energy (measured from 0.6 f s to 20 khz)* C40 db master volume parameter min typ max units step size (0 db to C46.5 db) line_out_l, line_out_r, mono_out 1.5 db output attenuation range span 46.5 db mute attenuation of 0 db fundamental* 75 db analog output parameter min typ max units full-scale output voltage 1 v rms 2.83 v p-p output impedance* 800 w external load impedance 10 k w output capacitance* 15 pf external load capacitance 100 pf v ref 2.00 2.25 2.50 v v ref current drive 100 m a v refout 2.25 v v refout current drive 5ma mute click (muted output minus unmuted midscale dac output)* 5mv *guaranteed, not tested. specifications subject to change without notice.
static digital specifications parameter min typ max units high-level input voltage (v ih ): digital inputs 0.4 dv dd v low-level input voltage (v il ) 0.2 dv dd v high-level output voltage (v oh ), i oh = 2 ma 0.5 dv dd v low-level output voltage (v ol ), i ol = 2 ma 0.2 dv dd v input leakage current C10 10 m a output leakage current C10 10 m a power supply parameter min typ max units power supply rangeanalog 4.5 5.5 v power supply rangedigital 4.5 5.5 v power supply current 120 ma power dissipation 600 mw analog supply current 60 ma digital supply current 60 ma power supply rejection (100 mv p-p signal @ 1 khz)* (at both analog and digital supply pins, both adcs and dacs) C40 db clock specifications* parameter min typ max units input clock frequency 24.576 mhz recommended clock duty cycle 40 50 60 % power-down states parameter set bits min typ max units adcs and input mux power-down pr0 110 ma dacs power-down pr1 100 ma analog mixer power-down (v ref and v refout on) pr1, pr2 54 ma analog mixer power-down (v ref and v refout off) pr0, pr1, pr3 47 ma digital interface power-down* pr4 120 ma internal clocks disabled* pr0, pr1, pr4, pr5 85 ma adc and dac power-down pr0, pr1 85 ma v ref standby mode* pr0, pr1, pr2, pr4, pr5 55 ma total power-down pr0, pr1, pr2, pr3, pr4, pr5 220 m a reset ( low ) 250 m a *guaranteed, not tested. specifications subject to change without notice. C5C rev. 0 AD1819A
AD1819A C6C rev. 0 timing parameters (guaranteed over operating temperature range) parameter symbol min typ max units reset active low pulsewidth t rst_low 1.0 m s reset inactive to bit_clk start-up delay t rst2clk 162.8 ns sync active high pulsewidth t sync_high 0.0814 1.3 m s sync low pulsewidth t sync_low 19.5 m s sync inactive to bit_clk start-up delay t sync2clk 162.8 ns bit_clk frequency 12.288 mhz bit_clk period t clk_period 81.4 ns bit_clk output jitter* 750 ps bit_clk high pulsewidth t clk_high 32.56 40.7 48.84 ns bit_clk low pulsewidth t clk_low 32.56 40.7 48.84 ns sync frequency 48.0 khz sync period t sync_period 20.8 m s setup to falling edge of bit_clk t setup 15.0 ns hold from falling edge of bit_clk t hold 15.0 ns bit_clk rise time t rise clk 4ns bit_clk fall time t fall clk 4ns sync rise time t rise sync 4ns sync fall time t fall sync 4ns sdata_in rise time t rise din 4ns sdata_in fall time t fall din 4ns sdata_out rise time t rise dout 4ns sdata_out fall time t fall dout 4ns end of slot 2 to bit_clk, sdata_in low t s2_pdown 1.0 m s setup to trailing edge of reset (applies to sync, sdata_out) t setup2rst 15 ns rising edge of reset to hi-z delay t off 25 ns *output jitter is directly dependent on crystal input jitter. reset bit_clk t rst2clk t rst_low figure 1. cold reset sync bit_clk t sync_high t rst2clk figure 2. warm reset t clk_high bit_clk t clk_low sync t sync_high t sync_low t sync_period t clk_period figure 3. clock timing
AD1819A C7C rev. 0 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD1819A features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings* parameter min max units power supplies analog (av dd ) C0.3 6.0 v digital (dv dd ) C0.3 6.0 v input current (except supply pins) 10.0 ma analog input voltage (signal pins) C0.3 av dd + 0.3 v digital input voltage (signal pins) C0.3 dv dd + 0.3 v ambient temperature (operating) C40 +85 c storage temperature C65 +150 c *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide temperature package package model range description option* AD1819Ajst C40 c to +85 c 48-terminal tqfp st-48 *st = thin quad flatpack. environmental conditions ambient temperature rating t amb = t case C (p d q ca ) t case = case temperature in c p d = power dissipation in w q ca = thermal resistance (case-to-ambient) q ja = thermal resistance (junction-to-ambient) q jc = thermal resistance (junction-to-case) package u ja u jc u ca tqfp 76.2 c/w 17 c/w 59.2 c/w bit_clk sync t hold sdata_out t setup figure 4. data setup and hold bit_clk sync sdata_in t riseclk t risesync t risedin t risedout t fallclk t fallsync t falldin t falldout sdata_out figure 5. signal rise and fall time bit_clk sdata_out sync sdata_in slot 1 slot 2 write to 0x26 data pr4 dont care t s2_pdown note: bit_clk not to scale figure 6. ac-link, link low power mode timing reset sdata_out hi-z t setup2rst t off sdata_in, bit_clk figure 7. ate test mode warning! esd sensitive device
AD1819A C8C rev. 0 pin configuration 48-terminal tqfp (st-48) 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 av ss2 chain_in nc cs0 nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) line_out_r line_out_l cx3d rx3d filt_l filt_r afilt2 phone_in aux_l aux_r video_l cd_gnd dv dd1 xtl_in xtl_out sdata_out bit_clk sdata_in sync reset pc_beep nc = no connect afilt1 cd_r mic1 mic2 line_in_l mono_out AD1819A line_in_r cs1 cd_l video_r chain_clk dv ss1 dv ss2 dv dd2 v refout v ref av ss1 av dd1 av dd2 pin function descriptions digital i/o pin name tqfp i/o description xtl_in 2 i 24.576 mhz crystal or clock input xtl_out 3 o 24.576 mhz crystal output sdata_out 5 i serial data output. serial, time division multiplexed, AD1819A input stream bit_clk 6 o/i* bit clock input, 12.288 mhz serial data clock. daisy chain output clock sdata_in 8 o serial data input. serial, time division multiplexed, AD1819A output stream sync 10 i 48 khz fixed rate sample sync clock reset 11 i reset. ac-link master hardware reset *input if the AD1819A is configured as slave 1 or slave 2. daisy chain connections pin name tqfp i/o description cs0 45 i daisy chain codec select cs1 46 i daisy chain codec select chain_in 47 i daisy chain data input chain_clk 48 i/o* 24.576 mhz buffered clock input/output *output when configured as master. input when configured as slave 1 or slave 2.
AD1819A C9C rev. 0 analog i/o these signals connect the AD1819A component to analog sources and sinks, including microphones and speakers. pin name tqfp i/o description pc_beep 12 i pc beep. pc speaker beep pass-through phone_in 13 i phone. from telephony subsystem speakerphone or handset aux_l 14 i auxiliary input left channel aux_r 15 i auxiliary input right channel video_l 16 i video audio left channel video_r 17 i video audio right channel cd_l 18 i cd audio left channel cd_gnd 19 i cd audio analog ground sense for differential cd input cd_r 20 i cd audio right channel mic1 21 i microphone 1. desktop microphone input mic2 22 i microphone 2. second microphone input line_in_l 23 i line in left channel line_in_r 24 i line in right channel line_out_l 35 o line out left channel line_out_r 36 o line out right channel mono_out 37 o monaural output to telephony subsystem speakerphone filter/reference pin name tqfp i/o description v ref 27 o voltage reference filter v refout 28 o voltage reference output 5 ma drive (intended for mic bias) afilt1 29 o antialiasing filter capacitoradc right channel afilt2 30 o antialiasing filter capacitoradc left channel filt_r 31 o ac-coupling filter capacitoradc right channel filt_l 32 o ac-coupling filter capacitoradc left channel rx3d 33 o 3d phat stereo enhancementresistor cx3d 34 i 3d phat stereo enhancementcapacitor power and ground signals pin name tqfp i/o description dv dd1 1 i digital v dd 5.0 v dv ss1 4 i digital gnd dv ss2 7 i digital gnd dv dd2 9 i digital v dd 5.0 v av dd1 25 i analog v dd 5.0 v av ss1 26 i analog gnd av dd2 38 i analog v dd 5.0 v av ss2 42 i analog gnd no connects pin name tqfp i/o description nc 39 no connect nc 40 no connect nc 41 no connect nc 43 no connect nc 44 no connect
AD1819A C10C rev. 0 m 0x02 mm mmm m 0x06 0 x 74 s s s s s oscillators xtl_out xtl_in gam 0x18 lov om g = gain a = attenuate m = mute mv = master volume mic1 mic2 aux cd video phone_in mono_out pc_beep line_in s s s s s s m 0x0c phm ga 0x0c phv m 0x0a pcm ga 0x0a pcv s s s s gm 0x1c rim im gm 0x1c lim im ls/rs (0) ls (4) rs (4) ls (3) rs (3) ls (1) rs (1) ls/rs (6) rs (5) ls (2) rs (2) 0x1a s e l e c t o r ls/rs (7) ls (5) 0db/20db m20 0x0e 0x20 0x20 pop m 0x14 vm m 0x12 cm m 0x16 am m 0x10 lm m 0x0e mcm mix 0x20 gm 0 x 1c rim im stereo mix (l) mono mix stereo mix (r) s 3d 0x22 dp reset sync bit_clk sdata_out sdata_in line_out_l line_out_r m 0x02 mm rov om gam 0x18 16-bit sd dac 3d 0x22 dp 16-bit sd dac ac link sr1 0x7a 16-bit sd adc 16-bit sd adc gm 0 x 1c lim im sr0 0x78 lpbk 0x20 ga 0x14 lvv rvv ga 0x12 lcv rcv ga 0x16 lav rav ga 0x10 llv rla ga 0x0e mcv 0 1 a 0x06 mmv a 0x02 rmv a 0x02 lmv ms figure 8. block diagram register map
AD1819A C11C rev. 0 indexed control registers g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h 0 0t e s e rx4 e s3 e s2 e s1 e s0 e s9 d i8 d i7 d i6 d i5 d i4 d i3 d i2 d i1 d i0 d ih 0 0 4 0 h 2 0e m u l o v r e t s a mm mx 5 v m l4 v m l3 v m l2 v m l1 v m l0 v m lxx5 v m r4 v m r3 v m r2 v m r1 v m r0 v m rh 0 0 0 8 h 4 0d e v r e s e r xxx x xxxxx xxxxx xx x h 6 0o n o m e m u l o v r e t s a mm m m xx x xxxxxx 5 v m m4 v m m2 v m m2 v m m1 v m m0 v m mh 0 0 0 8 h 8 0d e v r e s e r xxx x xxxxx xxxxx xx x h a 0e m u l o v p e e b c pm c p xx x xxxxxxx 3 v c p2 v c p1 v c p0 v c px h 0 0 0 8 h c 0e m u l o v e n o h pm h p xx x xxxxxxx 4 v h p3 v h p2 v h p1 v h p0 v h ph 8 0 0 8 h e 0e m u l o v c i mm c m xx x xxxxx 0 2 mx 4 v c m3 v c m2 v c m1 v c m0 v c mh 8 0 0 8 h 0 1e m u l o v n i e n i lm lxx 4 v l l3 v l l2 v l l1 v l l0 v l lxxx4 v l r3 v l r2 v l r1 v l r0 v l rh 8 0 8 8 h 2 1e m u l o v d cm v cxx 4 v c l3 v c l2 v c l1 v c l0 v c lxxx4 v c r3 v c r2 v c r1 v c r0 v c rh 8 0 8 8 h 4 1e m u l o v o e d i vm vxx 4 v v l3 v v l2 v v l1 v v l0 v v lxxx4 v v r3 v v r2 v v r1 v v r0 v v rh 8 0 8 8 h 6 1e m u l o v x u am axx 4 v a l3 v a l2 v a l1 v a l0 v a lxxx4 v a r3 v a r2 v a r1 v a r0 v a rh 8 0 8 8 h 8 1l o v t u o m c pm oxx 4 v o l3 v o l2 v o l1 v o l0 v o lxxx4 v o r3 v o r2 v o r1 v o r0 v o rh 8 0 8 8 h a 1t c e l e s d r o c e r xxx x x 2 s l1 s l0 s l xxxxx 2 s r1 s r0 s rh 0 0 0 0 h c 1n i a g d r o c e rm ixxx 3 m i l2 m i l1 m i l0 m i l xxxx 3 m i r2 m i r1 m i r0 m i rh 0 0 0 8 h e 1d e v r e s e r xxx x xxxxx xxxxx xx x h 0 2e s o p r u p l a r e n e gp o pxd 3xxxx i ms mk b p l xxxxx xx h 0 0 0 0 h 2 2l o r t n o c d 3 xxx x xxxxxxxx 3 p d2 p d1 p d0 p dh 0 0 0 0 h 4 2d e v r e s e r xxx x xxxxx xxxxx xx x h 6 2t a t s / r t n o c n w o d - r e w o pxx5 r p4 r p3 r p2 r p1 r p0 r p xxxx f e rl n ac a dc d ah 0 0 0 0 h 8 2d e v r e s e r xxx x xxxxx xxxxx xx x h 2 7d e v r e s e r xxx x xxxxx xxxxx xx x h 4 7n o i t a r u g i f n o c l a i r e s t o l s 6 1 m g e r 2 m g e r 1 m g e r 0 e q r d n q r l d 2 q r l d 1 q r l d 0 xxxxx q r r d 2 q r r d 1 q r r d 0 h 0 0 0 7 h 6 7s t i b l o r t n o c c s i mz c a dxxxxr s l dxr s l a d o m n e 1 x r s 7 d 0 8 x r s 7 d xx r s r dxr s r ah 0 0 0 0 h 8 70 e t a r e l p m a s5 1 0 r s4 1 0 r s3 1 0 r s2 1 0 r s1 1 0 r s0 1 0 r s9 0 r s8 0 r s7 0 r s6 0 r s5 0 r s4 0 r s3 0 r s2 0 r s1 0 r s0 0 r sh 0 8 b b h a 71 e t a r e l p m a s5 1 1 r s4 1 1 r s3 1 1 r s2 1 1 r s1 1 1 r s0 1 1 r s9 1 r s8 1 r s7 1 r s6 1 r s5 1 r s4 1 r s3 1 r s2 1 r s1 1 r s0 1 r sh 0 8 b b h c 71 d i r o d n e v7 f6 f5 f4 f3 f2 f1 f0 f7 s6 s5 s4 s3 s2 s1 s0 sh 4 4 1 4 h e 72 d i r o d n e v7 t6 t5 t4 t3 t2 t1 t0 t7 v e r6 v e r5 v e r4 v e r3 v e r2 v e r1 v e r0 v e rh 3 0 3 5 notes 1. all registers not shown and bits containing an x are reserved. 2. odd register addresses are aliased to the next lower even address. 3. reserved registers should not be written. 4. zeros should be written to reserved bits.
AD1819A C12C rev. 0 reset (index 00h) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h 0 0t e s e rx4 e s3 e s2 e s1 e s0 e s9 d i8 d i7 d i6 d i5 d i4 d i3 d i2 d i1 d i0 d ih 0 0 4 0 note: writing any value to this register performs a register reset, which cause all registers to revert to their default values (except 74h, which controls the serial configuration). reading this register returns the id code of the part and a code for the type of 3d stereo enhancement. id [9:0] identify capability. the id field decodes the capabilities of AD1819A on the following: bit function AD1819A* id0 dedicated mic pcm in channel 0 id1 modem line codec support 0 id2 bass and treble control 0 id3 simulated stereo (mono to stereo) 0 id4 headphone out support 0 id5 loudness (bass boost) support 0 id6 18-bit dac resolution 0 id7 20-bit dac resolution 0 id8 18-bit adc resolution 0 id9 20-bit adc resolution 0 *the AD1819A contains none of the optional features identified by these bits. se [4:0] stereo en hancement. the 3d stereo enhancement field identifies the analog devices 3d phat stereo enhancement. master volume (index 02h) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h 2 0e m u l o v r e t s a mm mx 5 v m l4 v m l3 v m l2 v m l1 v m l0 v m lxx 5 v m r4 v m r3 v m r2 v m r1 v m r0 v m rh 0 0 0 8 rmv [4:0] right master volume control. the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of C46.5 db. rmv5 right master volume maximum attenuation. forces rmv [4:0] to all 1s, C46.5 db. lmv [4:0] left master volume control. the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of C46.5 db. lmv5 left master volume maximum attenuation. forces lmv [4:0] to all 1s, C46.5 db. mm master volume mute. when this bit is set to 1, the left and right channels are muted. mm xmv5 . . . xmv0 function 0 00 0000 0 db attenuation 0 01 1111 C46.5 db attenuation 0 1x xxxx C46.5 db attenuation 1 xx xxxx db attenuation master volume mono (index 06h) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h 6 0o n o m e m u l o v r e t s a mm m m xxxxxxxxx 5 v m m4 v m m3 v m m2 v m m1 v m m0 v m mh 0 0 0 8 mmv [4:0] mono master volume control. the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of C46.5 db. mmv5 mono master volume maximum attenuation C46.5 db. mmm mono master volume mute. when this bit is set to 1, the mono channel is muted.
AD1819A C13C rev. 0 mmm mmv5 . . . mmv0 function 0 00 0000 0 db attenuation 0 01 1111 C46.5 db attenuation 0 1x xxxx C46.5 db attenuation 1 xx xxxx db attenuation pc beep (index 0ah) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h a 0e m u l o v p e e b c pm c p xxxxxxxxx x 3 v c p2 v c p1 v c p0 v c pxh 0 0 0 8 pcv [3:0] pc beep volume control. the least significant bit represents 3 db attenuation. this register controls the output from 0 db to a maximum attenuation of C45 db. the pc beep is routed to the left and right line outputs even when AD1819A is in a reset state. this is so that power-on self test (post) codes can be heard by the user in case of a hardware problem with the pc. pcm pc beep mute. when this bit is set to 1, the channel is muted. pcm pcv3 . . . pcv0 function 0 0000 0 db attenuation 0 1111 C45 db attenuation 1 xxxx C db attenuation phone volume (index 0ch) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h c 0e m u l o v e n o h pm h p xxxxxxxxxx 4 v h p3 v h p2 v h p1 v h p0 v h ph 8 0 0 8 phv [4:0] phone volume. allows setting the phone volume attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to C34.5 db. the default value is 0 db, mute enabled. phm phone mute. when this bit is set to 1, the channel is muted. mic volume (index 0eh) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h e 0e m u l o v c i mm c m xxxxxxxx 0 2 mx 4 v c m3 v c m2 v c m1 v c m0 v c mh 8 0 0 8 mcv [4:0] mic volume gain. allows setting the mic volume attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to C34.5 db. the default value is 0 db, mute enabled. m20 microphone +20 db gain block 0 = disabled; gain = 0 db. 1 = enabled; gain = +20 db. mcm mic mute. when this bit is set to 1, the channel is muted. line in volume (index 10h) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h 0 1e m u l o v n i _ e n i lm lxx 4 v l l3 v l l2 v l l1 v l l0 v l l xxx 4 v l r3 v l r2 v l r1 v l r0 v l rh 8 0 8 8 rlv [4:0] right line in volume. allows setting the line in right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to C34.5 db. the default value is 0 db, mute enabled. llv [4:0] left line in volume. allows setting the line in left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to C34.5 db. the default value is 0 db, mute enabled. lm line in mute. when this bit is set to 1, the channel is muted.
AD1819A C14C rev. 0 cd volume (index 12h) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h 2 1e m u l o v d cm v cxx 4 v c l3 v c l2 v c l1 v c l0 v c l xxx 4 v c r3 v c r2 v c r1 v c r0 v c rh 8 0 8 8 rcv [4:0] right cd volume. allows setting the cd right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to C34.5 db. the default value is 0 db, mute enabled. lcv [4:0] left cd volume. allows setting the cd left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to C34.5 db. the default value is 0 db, mute enabled. cvm cd volume mute. when this bit is set to 1, the channel is muted. video volume (index 14h) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h 4 1e m u l o v o e d i vm vxx 4 v v l3 v v l2 v v l1 v v l0 v v l xxx 4 v v r3 v v r2 v v r1 v v r0 v v rh 8 0 8 8 rvv [4:0] right video volume. allows setting the video right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to C34.5 db. the default value is 0 db, mute enabled. lvv [4:0] left video volume. allows setting the video left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to C34.5 db. the default value is 0 db, mute enabled. vm video mute. when this bit is set to 1, the channel is muted. aux volume (index 16h) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h 6 1e m u l o v x u am axx 4 v a l3 v a l2 v a l1 v a l0 v a l xxx 4 v a r3 v a r2 v a r1 v a r0 v a rh 8 0 8 8 rav [4:0] right aux volume. allows setting the aux right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to C34.5 db. the default value is 0 db, mute enabled. lav [4:0] left aux volume. allows setting the aux left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to C34.5 db. the default value is 0 db, mute enabled. am aux mute. when this bit is set to 1, the channel is muted. pcm out volume (index 18h) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h 8 1e m u l o v t u o m c pm oxx 4 v o l3 v o l2 v o l1 v o l0 v o l xxx 4 v o r3 v o r2 v o r1 v o r0 v o rh 8 0 8 8 rov [4:0] right pcm out volume. allows setting the pcm right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to C34.5 db. the default value is 0 db, mute enabled. lov [4:0] left pcm out volume. allows setting the pcm left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to C34.5 db. the default value is 0 db, mute enabled. om pcm out volume mute. when this bit is set to 1, the channel is muted. volume table (index 0ch to 18h) mute x4 . . . x0 function 0 00000 +12 db gain 0 01000 0 db gain 0 11111 C34.5 db gain 1 xxxxx C db gain
AD1819A C15C rev. 0 record select control (index 1ah) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h a 1t c e l e s d r o c e r xxxxx 2 s l1 s l0 s l xxxxx 2 s r1 s r0 s rh 0 0 0 0 rs [2:0] right record select. ls [2:0] left record select. used to select the record source independently for right and left. see table for legend. the default value is 0000h, which corresponds to mic in. rs2 . . . rs0 right record source 0 mic 1 cd_r 2 video_r 3 aux_r 4 line_in_r 5 stereo mix (r) 6 mono mix 7 phone_in ls2 . . . ls0 left record source 0 mic 1 cd_l 2 video_l 3 aux_l 4 line_in_l 5 stereo mix (l) 6 mono mix 7 phone_in record gain (index 1ch) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h c 1n i a g d r o c e rm i xxx 3 m i l2 m i l1 m i l0 m i l xxxx 3 m i r2 m i r1 m i r0 m i rh 0 0 0 8 rim [3:0] right input mixer gain control. each lsb represents 1.5 db, 0000 = 0 db and the range is 0 db to +22.5 db. lim [3:0] left input mixer gain control. each lsb represents 1.5 db, 0000 = 0 db and the range is 0 db to +22.5 db. im input mute. 0 = unmuted, 1 = muted or C db gain. im xim3 . . . xim0 function 0 1111 +22.5 db gain 0 0000 0 db gain 1 xxxxx C db gain general purpose (index 20h) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h 0 2e s o p r u p l a r e n e gp o pxd 3 xxx x i ms mk b p l xxxxxxx h 0 0 0 0 lpbk loopback control. adc/dac digital loopback mode. ms mic select. 0 = mic1. 1 = mic2.
AD1819A C16C rev. 0 mix mono output select. 0 = mix. 1 = mic. 3d phat stereo enhancement. 0 = phat stereo is off. 1 = phat stereo is on. pop pcm output path. the pop bit controls the optional pcm out 3d bypass path (the pre- and post- 3d pcm outpaths are mutually exclusive). 0 = pre-3d. 1 = post-3d. the register should be read before writing to generate a mask for only the bit(s) that need to be changed. the default value is 0000h. 3d control (index 22h) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d * h 2 2l o r t n o c d 3 xxxxxxxxxxxx 3 p d2 p d1 p d0 p dh 0 0 0 0 dp [2:0] depth control. sets 3d depth phat stereo enhancement according to table below. dp3 . . . dp0 depth 00% 1 6.67% 14 93.33% 15 100% power-down control/status (index 26h) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h 6 2t a t s / l r t n c n w o d - r e w o pxx5 r p4 r p3 r p2 r p1 r p0 r p xxxx f e rl n ac a dc d ah 0 0 0 0 ready bits: the ready bits are read only, writing to ref, anl, dac, adc will have no effect. these bits indi- cate the status for the AD1819A subsections. if the bit is a one then that subsection is ready. ready is defined as the subsection able to perform in its nominal state. adc adc section ready to transmit data. dac dac section ready to accept data. anl analog gainuators, attenuators, and mixers ready. ref voltage references, v ref and v refout up to nominal level. pr [5:0] power-down bits. bits 0 and 1 are to be used individually rather than in combination with each other. the last bit pr3 can be used in combination with pr2 or by itself. power-down state set bits adcs and input mux power-down pr0 dacs power-down pr1 analog mixer power-down (v ref and v refout on) pr1, pr2 analog mixer power-down (v ref and v refout off) pr0, pr1, pr3 ac-link interface power-down pr4 internal clocks disabled pr0, pr1, pr4, pr5 adc and dac power-down pr0, pr1 v ref standby mode pr0, pr1, pr2, pr4, pr5 total power-down pr0, pr1, pr2, pr3, pr4, pr5
AD1819A C17C rev. 0 serial configuration (index 74h) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h 4 7n o i t a r u g i f n o c l a i r e s t o l s 6 1 m g e r 2 m g e r 1 m g e r 0 e q r d n q r l d 2 q r l d 1 q r l d 0 xxxxx q r r d 2 q r r d 1 q r r d 0 h 0 0 0 7 drrq0 master ac 97 codec dac right request. drrq1 slave 1 codec dac right request. drrq2 slave 2 codec dac right request. dlrq0 master ac 97 codec dac left request. dlrq1 slave 1 codec dac left request. dlrq2 slave 2 codec dac left request. drqen fills idle status slots with dac request reads, and stuffs dac requests into lsb of output address slot. (ac-link slot 1.) regm0 master codec register mask. regm1 slave 1 codec register mask. regm2 slave 2 codec register mask. slot16 enable 16-bit slots. if your system uses only a single AD1819A, you can ignore the register mask and the slave 1/slave 2 request bits. if you write to this register, write ones to all of the register mask bits. the request bits are read-only. the codec asserts each request bit when the corresponding dac channel can accept data in the next frame. these bits are snapshots of the codec state taken when the current frame began (effectively, on the rising edge of sync), but they also take notice of dac samples sent in the current frame. if you set the drqen bit, the AD1819A will fill all otherwise unused ac-link status address and data slots with the contents of register 74h. that makes it somewhat simpler to access the information, because you dont need to continually issue ac-link read commands to get the register contents. also, the dac requests are reflected in slot 1, bits (11 . . . 6). these bits are active lo. slot16 makes all ac-link slots 16 bits in length, formatted into 16 slots. miscellaneous control bits (index 76h) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h 6 7s t i b l o r t n o c c s i mz c a d xxxx r s l dxr s l a d o m n e 0 1 x r s 7 d 8 x r s 7 d xx r s r dxr s r ah 0 0 0 0 arsr adc right sample generator select. connects right adc channel to sr0 or sr1. 0 = sr0 selected. 1 = sr1 selected. drsr dac right sample generator select. connects right dac channel to sr0 or sr1. 0 = sr0 selected. 1 = sr1 selected. srx8d7 multiply sr1 rate by 8/7. srx10d7 multiply sr1 rate by 10/7. srx10d7 and srx8d7 are mutually exclusive; srx10d7 has priority if both are set. moden modem filter enable (left channel only). change only when dacs are powered down. alsr adc left sample generator select. connects left adc channel to sr0 or sr1. 0 = sr0 selected. 1 = sr1 selected. dlsr dac left sample generator select. connects left dac channel to sr0 or sr1. 0 = sr0 selected. 1 = sr1 selected. dacz zero-fill (vs. repeat sample) if dac is starved.
AD1819A C18C rev. 0 sample rate 0 (index 78h) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h 8 70 e t a r e l p m a s5 1 0 r s4 1 0 r s3 1 0 r s2 1 0 r s1 1 0 r s0 1 0 r s9 0 r s8 0 r s7 0 r s6 0 r s5 0 r s4 0 r s3 0 r s2 0 r s1 0 r s0 0 r sh 0 8 b b sr0 [15:0] writing to this register allows the user to program the sampling frequency from 7 khz (1b58h) to 48 khz (bb80h) in 1 hz increments. programming a value greater than 48 khz or less than 7 khz may cause unpredictable results. sample rate 1 (index 7ah) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h a 71 e t a r e l p m a s5 1 1 r s4 1 1 r s3 1 1 r s2 1 1 r s1 1 1 r s0 1 1 r s9 1 r s8 1 r s7 1 r s6 1 r s5 1 r s4 1 r s3 1 r s2 1 r s1 1 r s0 1 r sh 0 8 b b sr1 [15:0] writing to this register allows the user to program the sampling frequency from 7 khz (1b58h) to 48 khz (bb80h) in 1 hz increments. the sample rate may be multiplied by 8/7 or 10/7 by setting bits d6 and d5 in register 76h. vendor id (index 7chC7eh) g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h c 71 d i r o d n e v7 f6 f5 f4 f3 f2 f1 f0 f7 s6 s5 s4 s3 s2 s1 s0 sh 4 4 1 4 s [7:0] this register is ascii encoded to a. f [7:0] this register is ascii encoded to d. g e r m u n e m a n5 1 d4 1 d3 1 d2 1 d1 1 d0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dt l u a f e d h e 72 d i r o d n e v7 t6 t5 t4 t3 t2 t1 t0 t7 v e r6 v e r5 v e r4 v e r3 v e r2 v e r1 v e r0 v e rh 3 0 3 5 t [7:0] this register is ascii encoded to s. rev [7:0] revision register field contains the revision number. these bits are read-only and should be verified before accessing vendor-defined features. digital interface AD1819A ac-link digital serial interface protocol the AD1819A incorporates an ac 97 5-pin digital serial interface that links it to a digital controller. ac-link is a bidirecti onal, fixed rate, serial pcm digital stream. it handles multiple input, and output audio streams, as well as control register accesse s employ- ing a time division multiplexed (tdm) scheme. the ac-link architecture divides each audio frame into 12 outgoing and 12 incom- ing data streams, up to 20-bit sample resolution. the AD1819A uses 16-bit samples. the data streams include: ac 97 protocol ? tag 1 input and output ? control 2 output slots control register write port ? status 2 input slots control register read port ? pcm playback 2 output slots 2-channel composite pcm output stream ? pcm record data 2 input slots 2-channel composite pcm input stream synchronization of all ac-link data transactions is signaled by the ac 97 controller. the AD1819A drives the serial bit clock onto ac-link, which the ac 97 controller then qualifies with a synchronization signal to construct audio frames. sync, which is fixed at 48 khz, is derived by dividing down the serial bit clock (bit_clk) by 256. the bit_clk is fixed at 12.288 mhz. ac-link serial data is updated on each rising edge of bit_clk. the receiver of ac-link data, the AD1819A for outgo- ing data and the ac 97 controller for incoming data, samples each serial bit on the falling edge of bit_clk. sync must remain high for a minimum of 1 bit_clk up to a maximum duration of 16 bit_clks at the beginning of each audio frame. the first 16 bits of the audio frame is defined as the tag phase. the remainder of the audio frame is the data phase. the AD1819A uses sync to define the beginning of the audio frame.
AD1819A C19C rev. 0 the ac-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a valid tag for its correspondin g time slot within the current audio frame. a 1 in a given bit position of slot 0 indicates that the corresponding time slot within the cur- rent audio frame has been assigned to a data stream, and contains valid data. if a slot is tagged invalid, it is the responsi bility of the source of the data, (AD1819A for the input stream, ac 97 controller for the output stream), to stuff all bit positions with 0s during that slots active time. the AD1819A stuffs all invalid slots with zeros and ignores invalid input slots. additionally, for power savings, all clock, sync, and data signals can be halted. for multiple codec operations, the AD1819A supports an enhanced mode for communicating with up to two additional codecs. the slave 1 AD1819A codec uses slots 5 and 6, while slave 2 uses slots 7 and 8 as shown in the following diagram. slave 1 123456789101112 slot # .... sync outgoing streams incoming streams tag rsrvd rsrvd rsrvd cmd adr cmd data pcm left pcm right pcm left pcm right pcm left pcm right tag rsrvd rsrvd rsrvd pcm left pcm right pcm left pcm right pcm left pcm right status data status adr rsrvd rsrvd enhanced mode slave 2 data phase tag phase figure 9. standard bidirectional audio frame ac-link audio output frame (sdata_out) the audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting AD1819As dac inputs and control registers. as briefly mentioned earlier, each audio output frame supports up to twelve 20-bit outgoing data time slots. slot 0 is a special reserved time slot containing 16 bits that are used for ac-link protocol infrastructure. within slot 0 the first bit is a global bit (sdata_out slot 0, bit 15), which flags the validity for the entire audio frame. if the valid frame bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. the next 1 2-bit positions sampled by ac 97 indicate which of the corresponding 12 time slots contain valid data. in this way input dac data streams of differing sample rates can be transmitted across the ac-link at its fixed 48 khz audio frame rate. the following dia gram illustrates the time-slot-based ac-link protocol. end of previous audio frame time slot valid bits (1) = time slot contains valid pcm data tag phase 20.8 m s (48khz) data phase slot 1 slot 2 slot 3 slot 12 sync bit_clk codec ready slot(1) slot(2) slot(12) 0 0 0 19 0 19 00 0 19 19 12.2888mhz 81.4ns sdata_in figure 10. ac-link audio output frame a new audio output frame begins with a low-to-high transition of sync. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the AD1819A samples the assertion of sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising edge of bit_clk, the ac 97 controll er transitions sdata_out into the first bit position of slot 0 (valid frame bit). each new bit position is presented to ac-link on a rising edge of bit_clk, and subsequently sampled by AD1819A on the following falling edge of bit_clk. this sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.
AD1819A C20C rev. 0 valid frame slot (1) slot (2) ac 97 controller samples first sdata_out bit of frame here sync bit_clk sdata_out AD1819A samples sync assertion here end of previous audio frame figure 11. start of an audio output frame sdata_outs composite stream is msb justified (msb first) with all nonvalid slots bit positions stuffed with 0s by the ac 97 controller. the AD1819A ignores invalid slots. in the event that there are less than 20 valid bits within an assigned and valid time slot, the ac 97 controller always stuffs all trailing nonvalid bit positions of the 20-bit slot with 0s. the AD1819A ignores unused bits. as an example, consider an 8-bit sample stream being played out to one of the AD1819As dacs. the first 8-bit positions are pre - sented to the dac (msb justified), followed by the next 12 bit positions, which are stuffed with 0s by the ac 97 controller. when mono audio sample streams are output from the ac 97 controller, it is necessary that both left and right stream time slot s be filled with the same data. slot 1: command address port the command port is used to control features and request status (see audio input frame slots l and 2) for AD1819A functions including, but not limited to, mixer settings and power management (refer to the control register section of this specification ). the control interface architecture supports up to sixty-four 16-bit read/write registers, addressable on even byte boundaries. only the even registers (00h, 02h, etc.) are valid, odd register (01h, 03h, etc.) accesses are discouraged (defaulting to the preceding even byte boundaryi.e., a read to 01h will return the 16-bit contents of 00h). note that shadowing of the control register file on the a c 97 controller is an option left open to the implementation of the ac 97 controller. the AD1819As control register file is readab le as well as writable. audio output frame slot 1 communicates control register address, and write/read command information to AD1819A. command address port bit assignments: bit (19) read/write command (1 = read, 0 = write) bit (18:12) control register index (64 16-bit locations, addressed on even byte boundaries) bit (11:0) reserved (stuffed with 0s) the first bit (msb) sampled by the AD1819A indicates whether the current control transaction is a read or a write operation. th e following 7-bit positions communicate the targeted control register address. the trailing 12-bit positions within the slot are reserved. slot 2: command data port the command data port is used to deliver 16-bit control register write data in the event that the current command port operatio n is a write cycle (as indicated by slot 1, bit 19). bit (19:4) control register write data (stuffed with 0s if current operation is not a write) bit (3:0) reserved (stuffed with 0s) if the current command port operation is not a write, the entire slot time should be stuffed with 0s by the ac 97 controller. slot 3: pcm playback left channel audio output frame slot 3 is the composite digital audio left playback stream. in a typical games compatible pc this slot is com- posed of standard pcm (.wav) output samples digitally mixed (on the ac 97 controller or host processor) with music synthesis output samples. if a sample stream of resolution less than 20 bits is transferred, the ac 97 controller should stuff all trail ing nonvalid bit positions within this time slot with 0s. slot 4: pcm playback right channel audio output frame slot 4 is the composite digital audio right playback stream. in a typical games compatible pc this slot is composed of standard pcm (.wav) output samples digitally mixed (on the ac 97 controller or host processor) with music synthesi s output samples. if a sample stream of resolution less than 20 bits is transferred, the ac 97 controller should stuff all trailing nonvalid bit positions within this time slot with 0s.
AD1819A C21C rev. 0 slot 5Cslot 8: multicodec communication ? slot 5 slave 1 pcm playback left channel ? slot 6 slave 1 pcm playback right channel ? slot 7 slave 2 pcm playback left channel ? slot 8 slave 2 pcm playback right channel slot 6Cslot 12: reserved audio output frame slot 6 to slot 12 are reserved for future use and should always be stuffed with 0s by the digital controller . ac-link audio input frame (sdata_in) the audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the ac 97 control ler. as is the case for audio output frame, each ac-link audio input frame consists of twelve 20-bit time slots. slot 0 is a special reserved time slot containing 16 bits used for ac-link protocol infrastructure. within slot 0 the first bit is a global bit (sdata_in slot 0, bit 15) which flags whether or not AD1819A is in the codec ready state. if the codec ready bit is a 0, this indicates that AD1819A is not ready for normal operation. this condition is normal fol- lowing the deassertion of power-on reset, for e xample, while a d1819as voltage references settle. when the ac-link codec ready indicator bit is a 1, it indicates that the ac-link and AD1819A control and status registers are in a fully operational state a nd all subsections are ready. prior to any attempts at putting AD1819A into operation the ac 97 controller s hould poll the first bit in the audio input frame (sdata_in slot 0, bit 15) for an indication that the AD1819A has asserted codec ready. once the AD1819A is sampled, codec ready is asserted the next 12-bit positions sampled by the ac 97 controller indicate which of the corresponding 12 time slots are assigned to input data streams and that they contain valid data. the following diagram illustrates the time-slot-based ac-link protocol. end of previous audio frame time slot valid bits ( 1 ) = time slot contains valid pcm data tag phase 20.8 m s (48khz) data phase slot 1 slot 2 slot 3 slot 12 sync bit_clk slot(1) slot(2) slot(12) 0 0 0 19 0 19 00 0 19 19 12.288mhz 81.4ns sdata_in ready codec figure 12. ac-link audio input frame a new audio input frame begins with a low-to-high transition of sync. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the AD1819A samples the assertion of sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising of bit_clk, the AD1819A transitions sdata_in i nto the first bit position of slot 0 (codec ready bit). each new bit position is presented to ac-link on a rising edge of bit_clk, and subsequently sampled by the ac 97 controller on the following falling edge of bit_clk. this sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams, are time aligned. slot (1) slot (2) ac 97 controller samples first sdata_in bit of frame here sync bit_clk sdata_in AD1819A samples sync assertion here end of previous audio frame codec ready figure 13. start of an audio input frame sdata_ins composite stream is msb justified (msb first) with all nonvalid bit positions (for assigned and/or unassigned time slots) stuffed with 0s by AD1819A. slot 0: tag phase sdata_in the AD1819A is capable of sampling data from 7 khz to 48 khz with a resolution of 1 khz. to enable a sample rate other than the default 48 khz, set the drqen bit (register 74h bit 11). this allows dac request bits (these are low active) to be output on th e sdata_in stream. the digital controller should monitor the adc valid bits to determine when the codec has valid data ready to send.
AD1819A C22C rev. 0 tag phase bit assignments: bit (15) codec ready bit (14) slot 1 valid bit (13) slot 2 valid bit (12) slot 3 valid/adc left data is valid on slot 3 bit (11) slot 4 valid/adc right data is valid on slot 4 bit (10) slot 5 valid/adc left data slave 1 valid on slot 5 bit (9) slot 6 valid/adc right data slave 1 valid on slot 6 bit (8) slot 7 valid/adc left data slave 2 valid on slot 7 bit (7) slot 8 valid/adc right data slave 2 valid on slot 8 bit (6:0) not used slot 1: status address port the status port is used to monitor status for AD1819A functions including, but not limited to, mixer settings and power manage- ment. audio input frame slot 1s stream echoes the control register index, for historical reference, for the data to be returned in s lot 2 (assuming that slots 1 and 2 had been tagged valid by the AD1819A during slot 0). status address port bit assignments: bit (19) reserved (stuffed with 0) bit (18:12) control register index (echo of register index for which data is being returned) bit (11) dac request slot 3 (0 = request, 1 = no request) bit (10) dac request slot 4 (0 = request, 1 = no request) bit (9) dac request slot 5 (0 = request, 1 = no request); slave 1 bit (8) dac request slot 6 (0 = request, 1 = no request); slave 1 bit (7) dac request slot 7 (0 = request, 1 = no request); slave 2 bit (6) dac request slot 8 (0 = request, 1 = no request); slave 2 bit (5:0) reserved (stuffed with 0s) the first bit (msb) generated by the AD1819A is always stuffed with a 0. the following 7-bit positions communicate the associat ed control register address, and the trailing 12-bit positions are stuffed with 0s by the AD1819A. slot 2: status data port the status data port delivers 16-bit control register read data. bit (19:4) control register read data (stuffed with 0s if tagged invalid by AD1819A) bit (3:0) reserved (stuffed with 0s) if slot 2 is tagged invalid by the AD1819A, the entire slot will be stuffed with 0s by the AD1819A. slot 3: pcm record left channel audio input frame slot 3 is the left channel output of the AD1819As input mux, post-adc. AD1819A transmits its adc output data (msb first), and stuffs the trailing nonvalid bit positions with 0s to fill out its 20-bi t time slot. slot 4: pcm record right channel audio input frame slot 4 is the right channel output of the AD1819As input mux, post-adc. AD1819A transmits its adc output data (msb first), and stuffs the trailing nonvalid bit positions with 0s to fill out its 20-bi t time slot. slot 5Cslot 8: multicodec communication ? slot 5 slave 1 pcm record left channel ? slot 6 slave 1 pcm record right channel ? slot 7 slave 2 pcm record left channel ? slot 8 slave 2 pcm record right channel slot 9Cslot 12: reserved audio input frame slots 9C12 are reserved for future use and are always stuffed with 0s by the AD1819A. ac-link low power mode the ac-link signals can be placed in a low power mode. when the AD1819As power-down register (26h) is programmed to the appropriate value, both bit_clk and sdata_in will be brought to a logic low voltage level.
AD1819A C23C rev. 0 slot 12 previous frame tag sdata_in bit_clk sync sdata_out slot 12 previous frame tag write to 0x26 data pr4 note: bit_clk not to scale figure 14. ac-link power-down timing bit_clk and sdata_in are transitioned low immediately following the decode of the write to the power-down register (26h) with pr4. when the ac 97 controller driver is at the point where it is ready to program the ac-link into its low power mode, s lots (1 and 2) must be the only valid stream in the audio output frame. the ac 97 controller should also drive sync and sdata_out low after programming AD1819A to this low power halted mode. once AD1819A has been instructed to halt bit_clk, a special wake-up protocol must be used to bring the ac-link to the active mode, since normal audio output and input frames can not be communicated in the absence of bit_clk. waking up the ac-link there are two methods for bringing the ac-link out of a low power, halted mode. regardless of the method, it is the ac 97 controller that performs the wake-up task. ac-link protocol provides for a cold ac 97 reset, and a warm ac 97 reset. the current power-down state would ultimately dictate which form of ac 97 reset is appropriate. unless a cold or register reset (a write to the reset registe r) is performed, wherein the AD1819A registers are initialized to their default values, registers are required to keep state during a ll power- down modes. the serial configuration register (0x74) maintains state during a register reset. once powered down, reactivation of the ac-link via reassertion of the sync signal may be immediate. when the AD1819A powers up, it indicates readiness via the codec ready bit (input slot 0, bit 15). cold ac 97 reset a cold reset is achieved by asserting reset for at least the minimum specified time. sync and sdata_in should be held low during the rising edge of reset . by driving reset , bit_clk and sdata_in will be activated, and all AD1819A control registers will be initialized to their default power-on reset values. reset is an asynchronous AD1819A input. warm ac 97 reset a warm ac 97 reset will reactivate the ac-link without altering the current AD1819A register values. a warm reset is signaled by driving sync high for a minimum of 1 m s in the absence of bit_clk. within normal audio frames sync is a synchronous AD1819A input. in the absence of bit_clk, however, sync is treated as an asynchronous input used in the generation of a warm reset to the AD1819A.
AD1819A C24C rev. 0 multiple code configuration setting up multiple codecs the AD1819A may be used with up to two additional ad1819 or AD1819A codecs. in order to configure the codecs as mas- ter, slave 1 or slave 2, refer to the following table. cs1 cs0 configuration 0 0 slave 1 codec 0 1 slave 2 codec 1 0 master codec 1 1 ac 97 mode codec 0 = ground; 1 = v dd . the xtal_in pin on the slave codecs must be tied to ground and the chain_in pin must be tied to ground on the last codec slave 1 (on a 2-codec design) or slave 2 (on a 3-codec design). see figures 15, 16 and 17. configure the codec resources programing regm (2:0) bits in the serial configuration regis- ter (74h) allows the digital controller read write access to all the internal registers on each codec according to the following table. regm2 regm1 regm0 read write 00 0 xx 0 0 1 master master 0 1 0 slave 1 slave 1 0 1 1 master master, slave 1 1 0 0 slave 2 slave 2 1 0 1 master master, slave 2 1 1 0 slave 1 slave 1, slave 2 1 1 1 master m aster, slave 1, slave 2
AD1819A C25C rev. 0 reset sdata_out sdata_in sync bit_clk cs0 cs1 chain_in chain_clk digital controller dv dd 10 m f tant 100nf 10 m f tant 100nf 100nf 10 m f tant 100nf 10 m f tant +5av dd +5av dd +5dv dd +5dv dd av dd2 av ss2 av dd1 av ss dv ss1 dv dd1 dv ss2 dv dd2 afilt1 afilt2 filt_l phone_in mono_out line_out_r line_out_l 1 m f 1 m f 1 m f 1 m f 47k v 47k v 47k v 1 m f 24.576mhz 22pf np0 22pf np0 10 m f tant 100nf 47nf 2.25v dc 100nf 1 m f 270pf np0 270pf np0 filt_r cx3d rx3d v refout v ref xtal_in xtal_out 600z analog ground digital ground AD1819A pc_beep line_in_r line_in_l mic1 mic2 cd_r cd_l cd_gnd video_l video_r aux_l aux_r 1 m f 1 m f 1 m f 1 m f 1 m f 1 m f 1 m f 7 36 34 33 27 1.37k v 47 48 4.99k v 100nf 100nf 1 m f 1 m f 1 m f 1 m f 28 figure 15. recommended one codec application circuit applications circuits the AD1819A has been designed to require a minimum amount of external circuitry. the recommended applications circuits are shown in figures 15C18. reference designs for the AD1819A are available and may be obtained by contacting your local analog devices sales representative or authorized distributor. example shell programs for establishing a communications path between the AD1819A and an adsp-21xx dsp are also available.
AD1819A C26C rev. 0 reset sdata_out sdata_in sync bit_clk cs0 cs1 chain_in chain_clk AD1819A master xtal_in xtal_out 22pf np0 22pf np0 24.576mhz fl0 dt0 dr0 rfs0 sclk0 sport0 reset sdata_out sdata_in sync bit_clk dv dd digital controller (adsp-2181) dv dd reset sdata_out sdata_in sync bit_clk cs0 cs1 chain_in chain_clk AD1819A slave 1 xtal_in xtal_out reset sdata_out sdata_in sync bit_clk cs0 cs1 chain_in chain_clk AD1819A slave 2 xtal_in xtal_out figure 16. three codec system example
AD1819A C27C rev. 0 reset sdata_out sdata_in sync bit_clk cs0 cs1 chain_in chain_clk AD1819A master xtal_in xtal_out 22pf np0 22pf np0 24.576mhz fl0 dt0 dr0 rfs0 sclk0 sport0 reset sdata_out sdata_in sync bit_clk digital controller (adsp-2181) dv dd reset sdata_out sdata_in sync bit_clk cs0 cs1 chain_in chain_clk AD1819A slave 1 xtal_in xtal_out figure 17. two codec system example 2.21k v * 100 v 100nf 10nf* nc mic1** mic2 AD1819A v refout fb 100pf 200hz < frequency response < 5khz @ C3db notes: *may need to optimize to suit microphone **select mic1 and max gain 20db +12db for 10mv rms microphone output. mic input . 10mv rms (mean) figure 18. microphone input
AD1819A C28C rev. 0 c3261C8C3/98 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 48-terminal tqfp (st-48) 0.354 (9.00) bsc 0.276 (7.0) bsc 1 12 13 25 24 36 37 48 top view (pins down) 0.276 (7.0) bsc 0.354 (9.00) bsc 0.011 (0.27) 0.006 (0.17) 0.019 (0.5) bsc seating plane 0.063 (1.60) max 0 min 0 C 7 0.006 (0.15) 0.002 (0.05) 0.030 (0.75) 0.018 (0.45) 0.057 (1.45) 0.053 (1.35) 0.030 (0.75) 0.018 (0.45) 0.007 (0.18) 0.004 (0.09)

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